
`define PADWIDTH 3  // Global width; controls parameter values.
                    // No reference to PADWIDTH except at top.
module tb;
  
  // The parameter definitions in TestBench are redundant,
  // because testbench will not be synthesized.
  // Changing testbench param values will override the
  // values in the design, which become defaults when
  // the design is instantiated in the testbench module:
  //
  parameter WIDTH = `PADWIDTH , PAD_NUM = 3;
  //
  wire[WIDTH-1+PAD_NUM:0] CountTest;
  reg count_enableTest,
      clockTest,    
      CountResetTest,
      OutEnableTest;
  
  // Design instance:
  param_counter_top
      #(.WIDTH(WIDTH), .PAD_NUM(PAD_NUM)) // Pass testbench size to design.
    u_param_counter_top (
         .count         (CountTest        ),
         .count_enable  (count_enableTest ),
         .clock         (clockTest        ),
         .count_reset   (CountResetTest   ),
         .out_enable    (OutEnableTest    )
       );
  
  initial
    begin
    #01 clockTest        = 1'b0;
        count_enableTest = 1'b0;
        CountResetTest   = 1'b0;
        OutEnableTest    = 1'b0;
    #02 CountResetTest   = 1'b1;
    #02 CountResetTest   = 1'b0;
    //
    #01 count_enableTest = 1'b1;
    #02 OutEnableTest    = 1'b1;
    // Later, we shall see better ways to
    // define a clock:
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #01 OutEnableTest    = 1'b0;
    #02 OutEnableTest    = 1'b1;
    #05 clockTest        = 1'b1;  // clock skips #3 here.
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #05 clockTest        = 1'b0;
    #05 clockTest        = 1'b1;
    #10 $finish;
    end
    initial begin
      $vcdpluson();
    end
  
endmodule // tb
